The present invention generally relates to the field of semiconductors, and more particularly relates to vertical field-effect-transistors having a silicided bottom source/drain.
Vertical transistors are a promising option for technology scaling for 5 nm and beyond. However, the contact has to land on the bottom source/drain to get the bottom source/drain connect to back end wiring. The distance to the bottom contact area to transistor will increase the resistance. A metal silicide on top of the source/drain can help mitigate this resistance penalty. However, the silicidation process is very difficult for the area between fins due to the tight fin pitch and results in metal sticking between fins, which causes defect or device variation.